A system controller connects memory and a Peripheral Component Interconnect (PCI) bus together. In one instance, the controller is considered a PCI target and another device on the PCI bus that initiates a read transaction is referred to as a PCI master. The term prefetch refers to the PCI target reading data in anticipation that the PCI master will not terminate the read transaction immediately after a first data phase is completed.
The PCI target may disconnect after the first data phase, but doing so leads to inefficient use of the PCI bus. It is more efficient for the PCI target to burst the data across the PCI bus until the master terminates the PCI transaction.
The system controller supports bursting by prefetching data from memory. In one example, the first four bytes of data is technically not a prefetch, since the PCI master device requests a minimum of four bytes (assuming 32 bit PCI bus). Any additional data read beyond the first four bytes before the PCI master has requested it is considered the prefetched data.
Not all memory transactions require prefetching or the same amount of prefetching. Excessive prefetching needlessly consumes bandwidth on the memory interface, internal busses within the system controller, as well as in a coherent system, the bus where snooping takes place.
The present invention addresses this and other problems associated with the prior art.